SAA7129AH/V1,518

Product Summary

The SAA7129AH/V1,518 is a Digital video encoder. The SAA7129AH/V1,518 encodes digital CB-Y-CR video data to an NTSC, PAL or SECAM CVBS or S-video signal. The circuit at a 54 MHz multiplexed digital D1 input port accepts two ITU-R BT.656 compatible CB-Y-CR data streams with 720 active pixels per line in 4:2:2 multiplexed formats, for example MPEG decoded data with overlay and MPEG decoded data without overlay, whereas one data stream is latched at the rising, the other one at the falling clock edge. The SAA7129AH/V1,518 includes a sync/clock generator and on-chip DACs.

Parametrics

SAA7129AH/V1,518 absolute maximum ratings: (1)VDDD, digital supply voltage: -0.5 to +4.6 V; (2)VDDA, analog supply voltage: -0.5 to +4.6 V; (3)Vi(A), input voltage at analog inputs: -0.5 to +4.6 V; (4)Vi(n), input voltage at pins XTALI, SDA and SCL: -0.5 to VDDD + 0.5 V; (5)Vi(D), input voltage at digital inputs or I/O pins outputs in 3-state: -0.5 to +4.6 V; outputs in 3-state: -0.5 to +5.5 V; (6)△VSS, voltage difference between VSSA(n) and VSSD(n): 100 mV max; (7)Tstg, storage temperature: -65 to +150 ℃; (8)Tamb, ambient temperature: 0 to 70 ℃; (9)Vesd, electrostatic discharge voltage Human body model: ±2000 to ±4000 V; Machine model: ±200 to ±400 V.

Features

SAA7129AH/V1,518 features: (1)Monolithic CMOS 3.3 V device, 5 V I2C-bus optional; (2)Digital PAL/NTSC/SECAM encoder; (3)System pixel frequency 13.5 MHz; (4)54 MHz double-speed multiplexed D1 interface capable of splitting data into two separate channels (encoded and baseband); (5)Three Digital-to-Analog Converters (DACs) for CVBS(CSYNC), VBS(CVBS) and C (CVBS) two times; (6)oversampled with 10-bit resolution (signals in brackets optional); (7)Three DACs for RED (CR), GREEN (Y) and BLUE (CB) two times oversampled with 9-bit resolution (signals in brackets optional); (8)Alternatively, an advanced composite sync is available on the CVBS output for RGB display centring; (9)Real-time control of subcarrier; (10)Cross-colour reduction filter; (11)Copy Generation Management System (CGMS) encoding (CGMS described by standard CPR-1204 of EIAJ); 20 bits in lines 20/283 (NTSC) can be loaded via I2C-bus Fast I2C-bus control port (400 kHz); (12)Line 23 Wide Screen Signalling (WSS) encoding; (13)Video Programming System (VPS) data encoding in line 16 (50/625 lines counting); (14)Encoder can be master or slave; (15)Programmable horizontal and vertical input; (16)synchronization phase; (17)Programmable horizontal sync output phase.

Diagrams